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Saturday, April 2, 2011

Accelerometer Registers, Setup and Use Part 1

To receive analog input, the pin connect block must first be configured to enable pins to operate in ADC mode.  For ease of wiring the student would like to use the GPIO pins 1 and 2 as ADC input pins.  These are the same pins as AD0.3 and AD0.2 (A/D converter inputs 3 and 2).  According to table 61 of the LPC214x User Guide(1), these two pins can be changed by using the register PINSEL1, by changing bits 29:28 and bits 27:26 (both two bit values should be 01).  All other pins should not be changed. So the register PINSEL1 needs a mask 00010100000000000000000000000000b  or  0x14000000.   If the PINSEL1 is set by using the |= operator the mask will set two pins to ADC mode while not modifying any other pins. The student is not sure whether or not to use a standard assignment operator '=' or else to use the '|=' operator.

Table 254 of the LPC214x Users Guide (1), shows the registers that are part of the ADC system.  The AD0CR is the control register for the AD0 system (the AD1 system will not be used), the AD0CR will be discussed in more detail below.   The AD0GDR is the global data register, it contains the AD0 system's done-bit, and also contains the result of the last conversion completed.  The AD0STAT also contains the done-bit, the Overrun-bit for each channel, and the A/D interrupt flag.  The registers AD0DR2 and AD0DR3
are the data registers for the channels 2 and 3, which hold the latest conversion for each of the channels.

The A/D Control Register is explained in table 255 of the LPC214x Users guide.  The SEL collection of bits 7:0 specify which pins are to be sampled and converted.  In software mode (which is being used for this project) the value should be set to 0x01.  The CLKDIV bits 15:8 specify a divisor of VPB clock (PCLK) that results in a value of 4.5MHz or less.  Burst 16:16 enables repeated conversions when enabled, this will not be enabled for this project.  The CLKS  19:17 specifies either the length of a burst measurement, or bit precision of the resulting conversion,  this could probably be toyed with to produce different results.  Bit 20 is reserved and should be set to 0. The PDN bit, 21, enables or disables the ADC. Bits 23:22 are reserved.  The Start bits  26:24 control when A/D conversion is started.  The Edge bit, 27, is used by the Start bits to determine which edged of a signal to start sampling.  Bits 31:28 are reserved.

The following code is an example of how the ADC may be set up

// Begin Example Code Segment
// Set pins P1 and P2 as ADC pins (2 and 3)
PINSEL1 =  0x14000000;

// Configure ADC0 for use.
AD0CR = ( 0x01 << 0 ) | // SEL=1 (Software mode)
( ( Fpclk / 4000000 ) << 8 ) |  // CLKDIV  = PCLK / 4 MHz... Final ADC clock speed will be 4MHz
( 0 << 16 ) | // BURST = 0, no BURST, software controlled
( 0 << 17 ) |   // CLKS = 0, 11 clocks/10 bits
( 1 << 21 ) |   // PDN = 1, normal operation
( 0 << 22 ) |   // TEST1:0 = 00
( 0 << 24 ) |   // START = 0 A/D conversion stops
( 0 << 27 ); // EDGE = 0 (CAP/MAT singal falling,trigger A/D Conversion)
// End Example Code Segment

 (1) LPC214x Users Guide

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